The white marker is live even with capture disarmed. PORTC pixels are sampled once per AVR cycle only while PORTC capture is armed. The instruction map records one span per AVR instruction only while separately armed; release builds compile this debugger path out.
Raster breakpoint
Cycle breakpoints stop at the first AVR instruction boundary that reaches/crosses the selected cycle. SYNC triggers are driven by the emulated PORTB edge itself, so unusual or deliberately mistimed sync code is still caught. Click the beam to copy a cycle; Shift-click an instruction-mapped cycle to jump disassembly to that PC.
Cycle logic analyzer
Opt-in exact-cycle analyzer. SPI SCK/MOSI/MISO are reconstructed from the emulated byte transfer using its CPOL/CPHA/DORD mode and transfer duration. PORTC-event capture is off by default because the beam view already contains a complete per-cycle PORTC trace; enable it when a VCD needs individual PORTC writes.
Scanline CPU budget
Bars show actual scanline length relative to the 1820-cycle target. Red/late lines cross the budget marker. Per-line instruction attribution is collected only while armed.
Source
Click a line number to set a source breakpoint; Alt-click clears it.
Disassembly
Word
Opcode
Instruction
Memory Editor
Select a region and address.
FLASH writes intentionally disabled.
Export memory
Binary export is streamed through bounded READ_MEM calls over the CUzeboxEX API; large SPI-RAM dumps do not require buffering the complete dump in the browser or web server.
Graphical Memory Preview
Raw linear pixels; browser-side visualization, bytes still come through READ_MEM.
API Console commands pass unchanged to CUzeboxEX API
Cycle-correlated OCR2A writes. Click a row to jump disassembly and pin its beam location. The break trigger can run without history; no event ring is written unless history is armed.
SD card
Live protocol timeline
Snapshot-derived: command packet, response, block transfer and SPI-byte progress remain visible while single-stepping even with SD history disarmed.
Payload inspector
The outlined byte is the next block offset; the underline marks the last completed byte. Filesystem context is decoded from the same snapshot; backing comparison is fetched only when explicitly enabled.
Derived on request from the existing SD protocol ring. Bars show command packet span, R1 wait, token wait, 512-byte payload, CRC, and write-busy time. Click a sample to jump to its starting AVR PC/beam position.
Filesystem operation history
This view is reconstructed on request from SD protocol history. Click an operation to jump to its starting AVR PC/beam position and open its first VFAT sector in the payload inspector.
Raw SD transactions
Seq
Cycle
PC
Event
Command
Sector
R1
Latency
Deterministic SD interaction record / replay
Recording captures card-visible BYTE_START (MISO sample), BYTE_END (MOSI delivery), CS and reset events with exact relative cycle timestamps, preserving even a CS edge during an in-flight byte. Replay restores the captured initial SD state, returns the recorded MISO stream, validates MOSI/CS/reset ordering and timing, and bypasses VFAT; any divergence requests a debugger stop.
Fault injection
Read-only state inspection has no tracing cost. SD history/break conditions share one gate at the SD-byte boundary; Step Into/Over/Out refreshes both status and any protocol event generated by that instruction.
DWARF Variables
Locals / parameters
Name
Type
Value
Location
Globals
Name
Type
Value
Location
Pause first; register/SRAM scalars up to 8 bytes.
Raw Stack
Call Stack heuristic
#
Call
Return
Instruction
Breakpoints
Watchpoints
Memory access history
Seq
Abs cycle
Raster
PC
Access
Address
Value
Opt-in SRAM/I/O history. Watchpoints and history share one hot-path gate; with neither armed, debugger builds pay only the shared normally-not-taken branch. Set FLAG_MEMORY_TRACE=0 to remove the history ring entirely while keeping the debugger/watchpoints.