Card timing preset NORMAL exactly reproduces the original hardcoded CUzeboxEX values
Changing any timing value below automatically selects CUSTOM and resets the emulated card so the new model starts from a clean power-up/init state.
Timing characteristics
Live card state
Live protocol timeline read-only; no trace history required
The six command slots fill as the card parser receives them. Response wait, data token, 512-byte payload, CRC and write-busy phases are derived directly from the current SD state machine.
Block payload inspector snapshot-only; current or arbitrary VFAT sector
The outlined byte is the next payload offset and the underline is the last completed byte. Filesystem role/cluster/directory context is decoded from the snapshot. Enabling comparison performs a side-effect-free backing read; with comparison off no host backing file is opened.
Protocol trace and SD break triggers opt-in at the SPI-byte boundary
Break after R1:
Filesystem breaks:
SD transaction timing
Derived on request from the existing SD protocol ring; no second timing history is collected.
Filesystem operation history
Derived on demand from the existing protocol ring: no second history buffer is collected. Consecutive logical file sectors merge into one range even when the FAT chain is physically fragmented. Ownership is resolved against the current VFAT map.
Raw SD transactions
| Seq | Cycle | PC | Event | Command | Arg | Sector | R1 | Latency | State |
|---|
History and break conditions share one SD-byte gate. With history and all triggers off, the tracer does nothing; FLAG_SD_TRACE=0 removes the gate and ring entirely. Command breakpoints stop after the R1 response is produced, so argument, result, state transition and sector are all available.
Automated timing stress runner API-driven; no emulation hot-path code
python3 tools/sd_stress_runner.py --frames 900 --conformance --threshold read_wait_bytes=0:128 --expect-mem SRAM:0x10F:==:1
The runner can sweep one or more SD timing fields, binary-search the largest passing latency, export CSV/JSON results, and restore the original SD timing/trace state afterward. --conformance also fails a case on reconstructed protocol errors even if the ROM completes its frame budget. See documentation/web-debugger.md for options.
Deterministic interaction record / replay exact card-visible SPI stream; explicitly armed
Recording captures card-visible BYTE_START (MISO sample), BYTE_END (MOSI delivery), CS and reset events with exact relative cycle timestamps, preserving even a CS edge during an in-flight byte. Replay restores the captured initial SD state, returns the recorded MISO stream, validates MOSI/CS/reset ordering and timing, and bypasses VFAT; any divergence requests a debugger stop.
Deterministic fault injection explicitly armed; up to 8 independent rules
| Slot | State | Fault | Value | CMD | Sector | Mode | Fired | Last cycle |
|---|
R1_DELAY and TOKEN_DELAY values are extra SPI bytes; BUSY_EXTEND is extra milliseconds; R1_BITS/REJECT use an R1 bit mask. CMD_CRC and DATA_CRC accept value 1. ONCE disarms the rule after its first matching injection; PERSIST remains armed. Rules are evaluated only in the SD protocol phase they can affect.
Preset comparison
| Preset | Init | Command wait | Read / inter-sector wait | Write busy | CS-high | Init byte cadence |
|---|